Product Summary
The LCMXO640C-3FT256C is a member of MachXO Family. The MachXO family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). The MachXO is designed to meet the requirements of applications traditionally addressed by CPLDs and low capacity FPGAs: glue logic, bus bridging, bus interfacing, power-up control, and control logic. The device integrates the best features of CPLD and FPGA devices on a single chip. It is available in 256-ball ftBGA package.
Parametrics
Absolute maximum ratings: (1)Supply Voltage, VCC: -0.5 to 3.75V; (2)Supply Voltage, VCCAUX: -0.5 to 3.75V; (3)Output Supply Voltage VCCIO: -0.5 to 3.75V; (4)I/O Tristate Voltage Applied: -0.5 to 3.75V; (5)Dedicated Input Voltage Applied: -0.5 to 4.25V; (6)Storage Temperature (ambient): -65 to 150鈩? (7)Junction Temp. (Tj): +125鈩?
Features
Features: (1)Non-volatile, Infinitely Reconfigurable: Instant-on-powers up in microseconds; Single chip, no external configuration memory required; Excellent design security, no bit stream to intercept; Reconfigure SRAM based logic in milliseconds; SRAM and non-volatile memory programmable through JTAG port; Supports background programming of non-volatile memory; (2)Sleep Mode: Allows up to 100x static current reduction; (3)TransFR Reconfiguration (TFR): In-field logic update while system operates; (4)High I/O to Logic Density: 256 to 2280 LUT4s; 73 to 271 I/Os with extensive package options; Density migration supported; Lead free/RoHS compliant packaging; (5)Embedded and Distributed Memory: Up to 27.6 Kbits sysMEM Embedded Block RAM; Up to 7.5 Kbits distributed RAM; Dedicated FIFO control logic; (6)Flexible I/O Buffer: Programmable sysIO buffer supports wide range of interfaces: LVCMOS 3.3/2.5/1.8/1.5/1.2; LVTTL; PCI; LVDS, Bus-LVDS, LVPECL, RSDS; (7)sysCLOCK PLLs: Up to two analog PLLs per device; Clock multiply, divide, and phase shifting; (8)System Level Support: IEEE Standard 1149.1 Boundary Scan; Onboard oscillator; Devices operate with 3.3V, 2.5V, 1.8V or 1.2V.
Diagrams
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Image | Part No | Mfg | Description | Pricing (USD) |
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LCMXO640C-3FT256C |
Lattice |
CPLD - Complex Programmable Logic Devices 640 LUTs 159 IO 1.8/ 2.5/3.3V -3 Spd |
Data Sheet |
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Image | Part No | Mfg | Description | Pricing (USD) |
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LCMXO1200C-3B256C |
Lattice |
CPLD - Complex Programmable Logic Devices 1200 LUTs 211 I/O 1.8/2.5/3.3V -3 SPD |
Data Sheet |
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LCMXO1200C-3B256I |
Lattice |
CPLD - Complex Programmable Logic Devices 1200 LUTs 211 I/O 1.8/2.5/3.3V -3 SPD |
Data Sheet |
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LCMXO1200C-3BN256C |
Lattice |
FPGA - Field Programmable Gate Array 1200 LUTs 211 I/O 1.8/2.5/3.3V -3 SPD |
Data Sheet |
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LCMXO1200C-3BN256I |
Lattice |
FPGA - Field Programmable Gate Array 1200 LUTs 211 I/O 1.8/2.5/3.3V -3 SPD |
Data Sheet |
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LCMXO1200C-3FT256C |
Lattice |
CPLD - Complex Programmable Logic Devices 1200 LUTs 211 IO 1.8 /2.5/3.3V -3 Spd |
Data Sheet |
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LCMXO1200C-3FT256I |
Lattice |
CPLD - Complex Programmable Logic Devices 1200 LUTs 211 IO 1.8 /2.5/3.3V -3 Spd I |
Data Sheet |
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