Product Summary

The IBM25PPC750L-GB400A2T is targeted for high performance, low power systems and supports the following power management features: doze, nap, sleep, and dynamic power management. The IBM25PPC750L-GB400A2T consists of a processor core and an internal L2 Tag combined with a dedicated L2 cache interface and a 60x bus.

Parametrics

Absolute Maximum Ratings(1)Core supply voltage, VDD: -0.3 to 2.5 V; (2)PLL supply voltage, AVDD: -0.3 to 2.5 V; (3)L2 DLL supply voltage, L2AVDD -0.3 to 2.5 V; (4)60x bus supply voltage (maximum), OVDD(3.3V): -0.3 to 3.6V; (5)60x bus supply voltage (maximum), OVDD(2.5V): -0.3 to 2.8V; (6)60x bus supply voltage (maximum), OVDD(1.8V): -0.3 to 2.1V; (7)L2 bus supply voltage (maximum), L2OVDD: -0.3 to 3.6 V; (8)Input voltage (maximum), VIN(3.3V): -0.3 to 3.6 V; (9)Input voltage (maximum), VIN(2.5V): -0.3 to 2.8; (10)Input voltage (maximum), VIN(1.8V): -0.3 to 2.1; (11)Storage temperature range TSTG -55 to 150 掳C.

Features

Features: (1)Four instructions fetched per clock; (2)One branch processed per cycle (plus resolving 2 speculations); (3)Up to 1 speculative stream in execution, 1 additional speculative stream in fetch; (4)512-entry branch history table (BHT) for dynamic prediction; (5)64-entry, 4-way set associative branch target instruction cache (BTIC) for eliminating branch delay; (6)slots; (7)Full hardware detection of dependencies (resolved in the execution units); (8)Dispatch two instructions to six independent units (system, branch, load/store, fixed-point unit 1,; (9)fixed-point unit 2, or floating-point); (10)Serialization control (predispatch, postdispatch, execution, serialization); (11)Register file access; (12)Forwarding control; (13)Partial instruction decode; (14)One cycle load or store cache access (byte, half-word, word, double-word); (15)Effective address generation; (16)Hits under misses (one outstanding miss); (17)Single-cycle misaligned access within double word boundary; (18)Alignment, zero padding, sign extend for integer register file; (19)Floating-point internal format conversion (alignment, normalization); (20)Sequencing for load/store multiples and string operations; (21)Store gathering; (22)Cache and TLB instructions; (23)Big and little-endian byte addressing supported; (24)Misaligned little-endian support in hardware.

Diagrams

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